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General Features
The ATVaultIC460 is an ASSP designed to secure various systems against counterfeiting, cloning or identity theft. It is a hardware security module that can be used in many applications such as anti-cloning, access control or hardware protection. Cryptographic Services * Public Key Pair Generation * Digital Signature * Encryption / Decryption * Message Digest * Key Wrapping / Unwrapping * HOTP One-Time Password Generation * True Random Number Generation Software Features * FIPS 140-2 Identity-based authentication using password, Secure Channel Protocol (SCP02 / SCP03) or Microsoft(R) Minicard Driver strong authentication * Rights Management (Administrator, Approved User, Non-approved User...) * Embedded Dynamic FAT12 File System Communication * USB 2.0 Full Speed Certified, USB CCID compliant * High Speed Slave SPI Serial Interface, ATMEL Proprietary Protocol * IC (Two Wire Interface), ATMEL Proprietary Protocol * ISO7816 UART using T=0 or T=1 Protocols Hardware Platform * SecureAVR(R) 8-/16-bit RISC CPU * Hardware Random Number Generator * Hardware 3DES Crypto Accelerator (112bits keys) * Hardware AES Crypto Accelerator * Hardware 32-bit Public Key Crypto Accelerator
Notes: 1. Key sizes supported:
Cryptographic Algorithms * DES / 3DES * AES 128/192/256 bits * RSA up to 4096 bits(1) * DSA up to 2048 bits * ECC up to 384 bits Memory * EEPROM 128 Kbytes (for user) * Write Endurance 100 Kcycles * Data Retention 10 Years * 2ms Program + 2ms Erase Packages
VaultICTM Family ATVaultIC460 Technical Datasheet
* 44-QFN (RoHS compliant) * 8-SOIC (RoHS compliant)
Certifications / Standards * EAL4+ Ready * FIPS 140-2 Security Level 3 * Microsoft CSP minidriver compliant * SSL support * PKCS#11 * Microsoft MS-CAPI
- Linear key size up to 2888 bits for CRT format only (2240 bits otherwise) - 4096 bits for: CRT only Private exponent, Public exponent, CRT key generation
For more details about the alogrithms supported please refer to Table 2-1, "Supported Algorithms table," on page 8.
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Preliminary
This document is the complement to the "AT98SO Generic Datasheet" [1](TPR0395X- Available under Non-Disclosure Agreement only) for the ATVaultIC460. It only documents the values and set of features specific to this product.
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1. Overview
1.1 Tampering resistance
The proven technology used in ATVaultIC460 security modules is already widespread and used in national ID/health cards, e-passports, bank cards (storing user Personal Identification Number, account numbers and authentication keys among others), pay-TV access control and cell phone SIM cards (allowing the storage of subscribers' unique ID, PIN code, and authentication to the network), where cloning must definitely be prevented. More than one billion of Secure Microcontrollers addressing all these applications have been already sold by Atmel and successfully implemented in many secure systems. Atmel's security modules will advantageously replace complex and expensive proprietary antitampering protection system. Their advantages include low cost, ease of integration, higher security and proven technology. They are designed to keep contents secure and avoid leaking information during code execution. While on regular microcontrollers, measuring current consumption, radio emissions and other side channels attacks may give precious information on the processed data or allow the manipulation of the data. Atmel's secure microcontrollers' security features include voltage, frequency and temperature detectors, illegal code execution prevention, tampering monitors and protection against side channel attacks and probing. The chips can detect tampering attempts and destroy sensitive data on such events, thus avoiding data confidentiality being compromised. These features make cryptographic computations secure in comparison with regular microcontrollers whose memories can be easily duplicated. It is much safer to delegate cryptographic operations and storage of secret data (keys, identifiers, etc.) to an Atmel secure microcontroller.
1.2
Authentication capability
The methods to authenticate humans are generally classified into three cases: physical attribute (e.g. fingerprint, retinal pattern, facial scan, etc.), security device (e.g. ID card, security token, software token or cell phone) and something the user knows (e.g. a password/passphrase or a personal identification number). To fight against identity theft, the multi-factor authentication is a stronger alternative to the classical login/password authentication (called weak authentication). It combines two or more authentication methods (often a password combined with a security token). Two-factor systems greatly reduce the likelihood of fraud by requiring the presence of a physical device used together with a password. If the physical device is lost or the password is compromised, security is still intact. NIST's authentication guideline [1] can be referred to for further details. Multi-factor authentication requires a strong authentication. Anticloning is safely implemented through one-way or mutual strong authentication. Various authentication protocols exist (as specified in ISO9798-2 [3] or FIPS196 [4]), but the main method is the challenge response authentication: 1. The authenticator sends a challenge (e.g. a random number) to the equipment that must be authenticated ("the claimant"). 2. The claimant computes a digital signature of the combination of this challenge with an optional identifier, using a private or secret key. The requested signature is then returned to the authenticator.
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3. The authenticator checks the signature using either the same secret key or the public key associated to the claimant's private key and decides whether the claimant is authorized or not based on the signature verification result. This strong authentication method requires storing secret data. Pure software multi-factor solutions are thus not reliable. Numerous companies are now providing authentication solutions based on USB tokens. Tokens connected through USB are a convenient solution since they require no additional hardware. Atmel's turnkey USB Secure Microcontroller Solutions can help providers focus on their security model and their application without loosing too much time on tamper protection and other complex hardware security concerns.
1.3
Secure storage
If sensitive data is stored in files on a hard disk, even if those files are encrypted, the files can be stolen, cloned and subjected to various kinds of attacks (e.g. brute force or dictionary attack on passwords). Therefore secure microcontrollers-based hardware tokens are a must. Placing secrets outside the computer avoids risking exposure to malicious software, security breaches in web browsers, files stealing, etc.
1.4
Flexibility
The ATVaultIC460 product features: * Various communication interfaces including SPI (Serial Protocol Interface), I2C (Twisted Wire Interface), USB (Universal Serial Bus) and ISO7816 SmartCard interface. * Low pin count (Reset, Vcc, GND, and communication interface specific pins) making integration into an existing board simple. ATVaultIC460 modules are available in small packages (SOIC8 or QFN44) to fit into the most size-constrained devices. * Low power consumption, in order to extend battery life in portable devices and low-power systems. ATVaultIC460 devices consume less than 400A in standby mode, and only 10 to 20 mA during CPU-intensive operations depending on the required action. * Embedded firmware that provides advanced functions: - Secure storage: a fully user-defined non-volatile storage of sensitive or secret data. - Identity-based authentication with user, administrator and manufacturer roles supported. - Administration mode to manage user authentication data and security features - Manufacturer mode to initialize the file system content and module parameters. - Cryptographic command set to perform cryptographic operations using keys and data from the file system including: authentication, digital signature, encryption/decryption, hash, one-time password generation, random generation and public key pair generation. - Public domain cryptographic algorithms such as DES, 3DES, AES, RSA(R) PKCS#1 v2.1, DSA, EC-DSA, MAC using DES, 3DES or AES - Cryptographic protocols such as secret-key unilateral or mutual authentication [3] and public key based unilateral or mutual authentication [4]. - Secure Channel Protocol using 3DES or AES. - Robust communication protocol stacked over the physical communication interfaces.
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- Starter Kit with RSA(R) PKCS#11 [5] and Microsoft(R) MS-CAPI [6] libraries. Atmel's application note [7] presents examples of efficient and cost effective IP protection applications utilizing secure chips in various embedded systems.
1.5
Typical application
The ATVaultIC460 is a turnkey solution that combines powerful cryptographic capabilities and secure data storage. A typical application of the ATVaultIC460 is Video Slot Gaming Machines. Fraud, theft and embezzelment are the big fears of casinos so that they look for security inside their gaming machines. An ATVaultIC460 linked to the main processor of the machine allows authentication of the host controller (casino) and of the slot machine. Moreover physical protection of the sensitive code/ data, data encryption, secure communication channel, data integrity checking are other security features provided by the ATVaultIC460. Figure 1-1. Gaming Application
Gaming Machine
Casino Host Control
Main Processor
ATVaultIC460
For more details about the solution, please refer to the Application Note "How to secure Video Slot Gaming Machines using VaultICTM Security Modules?"[7].
1.6
1.6.1
Ordering Information
Legal A Non-Disclosure Agreement must be signed with ATMEL. An Export License for cryptographic hardware/software must be granted.
1.6.2
Quotation and Volume For the minimum order of quantity and the annual volume, please contact your local ATMEL sales office.
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1.6.3
Part Number
Reference ATVaultIC460-Z ATVaultIC460-R Description ATVaultIC460 chip in QFN44 package ATVaultIC460 chip in SOIC8 package (USB, SPI/IC or ISO7816 configuration)
ATVaultIC-STK02-460Z Starter Kit for ATVaultIC460 in QFN44 package ATVAULTIC-STK02-460R Starter Kit for ATVaultIC460 in SOIC8 package
1.6.4
Starter Kit The ATVaultIC Starter Kit provides an easy path to master the cryptographic and secure data storage features of the ATVaultIC secure modules. The content is : * ATVaultIC460 samples with 1 dedicated test socket * ATVaultIC460 USB dongles * 1 CD-ROM containing a support documentation set (getting started, application notes, reference design), some demo applications to get an insight into the ATVaultIC features, the "AT98 Manager" tool to design the file system and to personalize samples, a hardware independent cryptographic API with source code.
1.6.5
Demo Kit TBD
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1.7 Software and Hardware Architecture
The ATVaultIC460 software architecture is as exposed on the diagram below. Figure 1-2. Software and Hardware Architecture
Application Interface
Authentication
Crypto services
( MAC,Signature,...)
Application management Data storage
(File System)
&
Administration services
(Key management)
Crypto Library
(RSA, 3DES, AES...)
Memory
Management
Communication Stack
(T=0,T=1...)
ATVaultIC Hardware
TDES Public EEPROM Key AES Crypto secureAVR RAM Engine
RNG
CORE
USB 2.0
I2C
HS SPI
ISO 7816
Hardware Security
Power
Management
SPI / I2C / ISO7816 / USB
Device
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2. Detailed Features
2.1 Communication Interfaces
The ATVaultIC460 embeds the following communication interfaces: * USB 2.0 device full speed (up to 12 Mbps) * High Speed SPI: up to 16 Mbps * IC : up to 400 kbps * ISO7816 : up to 625 kbps
2.2
Security Mechanisms
The table below summarizes the cryptographic algorithms, and their identifiers, supported by the ATVaultIC460. Table 2-1. Cryptographic Services Supported Algorithms table Supported Algorithms * Generic: ISO/IEC 9798-2 / FIPS 196 unilateral authentication protocol ISO/IEC 9798-2 mutual authentication protocol Algo Identifiers
Strong Authentication
* Password authentication * Global Platform v2.2 Secure Channel 02 (SCP02) using 3DES * Global Platform v2.2 Secure Channel 03 (SCP03) using AES * Microsoft Card Minidriver * RSA key-pair generation * KGEN_RSA * KGEN_ECDSA * KGEN_DSA * ALG_MAC_ISO9797_ALG1_3DES_ EDE * ALG_MAC_ISO9797_ALG3_DES * ALG_CMAC_AES
-
-
Public Key-Pair Generation
* Elliptic Curves key-pair generation * DSA key-pair generation * ISO/IEC 9797-1 CBC-MAC algorithm 1 using 3DES with 112-bit keys * ISO/IEC 9797-1 CBC-MAC algorithm 3 using DES with 56-bit keys * NIST SP 800-38B AES CMAC
CMAC (Cipher-based Message Authentication Codes) HMAC (Hash-based Message Authentication Codes)
* FIPS 198 HMAC with SHA-1 or SHA-256 * PKCS#1 v2.1 RSASSA PSS
* ALG_HMAC * ALG_RSASSA_PKCS_PSS * ALG_RSASSA_PKCS * ALG_ECDSA * ALG_DSA
Message Signature
* PKCS#1 v2.1 RSASSA-PKCS1-v1_5 * FIPS 186-2 ECDSA * FIPS 186-2 DSA
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Cryptographic Services Supported Algorithms Block Ciphering: * DES * 3DES-EDE * 3DES-EEE * AES Block chaining modes: * ECB * CBC * OFB Message Encryption * CFB Padding methods: * No padding * Method 1 * Method 2 * PKCS 5 * PKCS 7 Encryption: * PKCS#1 v2.1 RSAES-OAEP * PKCS#1 v2.1 RSAES-PKCS1-v1.5 * Raw RSA X509 with no padding HOTP - One-Time Password Generation Message Digest Random Number Generation * FIPS 198 HMAC algorithm with SHA1 digest * SHA-1 * SHA-224 * SHA-256 * FIPS 140-2 LVL3 using 3DES * ALG_RSAES_PKCS_OAEP * ALG_RSAES_PKCS * ALG_RSAES_X509 * ALG_HOTP * ALG_SHA1 * ALG_SHA224 * ALG_SHA256 * PAD_NONE * PAD_METHOD_1 * PAD_METHOD_2 * PAD_PKCS5 * PAD_PKCS7 * CHA_ECB * CHA_CBC * CHA_OFB * CHA_CFB * ALG_DES * ALG_3DES_EDE * ALG_3DES_EEE * ALG_AES Algo Identifiers
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3. Product Characteristics
3.1 Command Timings (T=25C)
!
Caution
The table below includes only the ATVaultIC460 internal process. Communication protocol overhead and device-side process are excluded. Command Timings table Context Min. Typ. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
16+1 16+1
Table 3-1. Command
Max.
Unit ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms
(or batch of commands) Encryption / Decryption Encryption / Decryption Encryption / Decryption Encryption Encryption Encryption Decryption Decryption Decryption Decryption Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Verification Signature / Generation Signature / Generation Signature / Generation Signature / Generation Signature / Generation Signature / Generation Signature / Generation DES-ECB, 258 bytes data 3DES-ECB, 258 bytes data AES RSAES-OAEP 1024-bit RSA key, public exp 216+1 RSAES-OAEP 2048-bit RSA key, public exp 2 RSAES-OAEP 1024-bit RSA key, public exp 2 RSAES-OAEP 4096-bit RSA key, public exp 2 MAC DES algo 3 padding M2, 258 bytes data MAC DES algo 1 padding M2, 258 bytes data RSASSA-PSS 1024-bit RSA key, public exp 2 RSASSA-PSS 4096-bit RSA key, public exp 2 RSASSA-PSS 2048-bit RSA key, public exp 216+1
16+1
RSAES-OAEP 4096-bit RSA key, public exp 216+1
16+1
RSAES-OAEP 2048-bit RSA key, public exp 216+1
16+1
RSAES-OAEP 4096-bit RSA CRT key, public exp 216+1
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
16+1
RSASSA-PKCS-v1_5 1024-bit RSA key, public exp 216+1 RSASSA-PKCS-v1_5 2048-bit RSA key, public exp 2 DSA ECDSA MAC DES algo 3 padding M2, 258 bytes data MAC DES algo 1 padding M2, 258 bytes data RSASSA-PSS 1024-bit RSA key, public exp 2 RSASSA-PSS 4096-bit RSA key, public exp 2
16+1
RSASSA-PKCS-v1_5 4096-bit RSA key, public exp 216+1
TBD TBD TBD TBD TBD
16+1
RSASSA-PSS 2048-bit RSA key, public exp 216+1
16+1
RSASSA-PKCS-v1_5 1024-bit RSA key, public exp 216+1 RSASSA-PKCS-v1_5 2048-bit RSA key, public exp 2
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Command Context (or batch of commands) Signature / Generation Signature / Generation Signature / Generation Key Generation Key Generation Key Generation Key Generation Key Generation RSASSA-PKCS-v1_5 4096-bit RSA key, public exp 216+1 DSA ECDSA ECC RSA 1024-bits, public exp 2 RSA 4096-bits, public exp 2 DSA
16+1
Min.
Typ. TBD TBD TBD TBD
Max.
Unit ms ms ms ms
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD TBD TBD TBD
ms ms ms ms
RSA 2048-bits, public exp 216+1
16+1
3.2
Maximum Ratings
Table 3-2.
Absolute Maximum Ratings(1)
Operating Temperature ..................................................................................................... -25C to +85C Supply Voltage Vcc.............................................................................................................. -0.3V to +7.5V Input Voltage Vin ........................................................................................................Vss-0.3V to Vcc+0.3V Maximum Operating Voltage .............................................................................................................. 7.5V DC Current VCC and GND Pins.......................................................................................................... TBD Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3.3
AC/DC Characteristics (2.7V - 5.5V range; T= -25C to +85C)
Table 3-3.
Symbol VCC Vbat VMAX VMIN TMAX TMIN
AC/DC Characteristics (2.7V - 5.50V range; T= -25C to +85C)
Parameter Condition 3.0V (+/-10%) 5.0V (+/-10%) Min. 2.7 4.5 2.2 5.5 3.0V, 5.0V 85 -25 2.7 Typ. 3.0 5.0 3 Max. 3.3 5.5 3.5 V V C C Unit V
Supply Voltage Power Battery Voltage Monitor: high level detection Voltage Monitor: low level detection Temperature Monitor: high level detection Temperature Monitor: low level detection
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Symbol VIH VIL IIH IIL
Parameter Input High Voltage - I/O0,CLK,RST, MISO,MOSI,SCK, SPI_SEL, SS Input Low Voltage- - I/O0,CLK,RST, MISO,MOSI,SCK, SPI_SEL, SS Leakage High Current- I/O0,CLK,RST, MISO,MOSI,SCK, SPI_SEL, SS Leakage Low Current - I/O0,CLK,RST, MISO,MOSI,SCK, SPI_SEL, SS Output Low Voltage - I/O 0,SS Output Low Voltage - MISO, MOSI, SCK Output High Voltage - I/O 0,SS, MISO, MOSI, SCK Pin Pull-up I/O0, RST,SPI_SEL,SS SPI Clock (Input)
Condition
Min. 0.7*VCC VSS-0.3
Typ.
Max. VCC+0.3 0.2*VCC 10 10 0.08*VCC
Unit V V A A
VIN = VIH VIN = VIL
-10 -40 0
VOL
IOL =1mA 0 IOH = 1mA 0.7*VCC 220 Duty cycle=40% to 60% Cout=30pF Rpullup=20kOhm Cout=30pF Rpullup=20kOhm TBD 20 TBD 0.15*VCC VCC
V
VOH RI/O fSCK
V KOhm MHz
Tr Tf
I/O Output Rise Time (HRD Mode)
1
s
I/O Output Fall Time
1
s
- Chip in low power mode: * 400A when external clock supplied * 400A when no external clock is supplied (CLK signal in high state) - Chip awaken, no crypto running: * 6mA when external clock supplied * 10mA when no external clock is supplied (CLK signal in high state) - Additional consumption during RSA/ECC authentication: * 4mA when external clock supplied * 20mA when no external clock is supplied (CLK signal in high state) - Additional consumption during DES computations: * 4mA when external clock supplied * 10mA when no external clock is supplied (CLK signal in high state)
Icc
Typical Current at 25C
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3.4
3.4.1
Timings
IC Timings The table below describes the requirements for devices connected to the IC Bus. The ATVaultIC460 IC Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 3-1. Table 3-4.
Symbol tr tof fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF
IC Requirements
Parameter Rise Time for both SDA and SCL Output Fall Time from VIHmin to VILmax SCL Clock Frequency Hold Time (repeated) START Condition Low Period of the SCL Clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Condition Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max TBD TBD 100 TBD TBD TBD TBD TBD TBD TBD TBD Unit ns ns kHz s s s s s ns s s
Figure 3-1.
tof tLOW SCL tSU;STA SDA tHD;STA
IC Timings
tHIGH tLOW tr
tHD;DAT
tSU;DAT
tSU;STO
tBUF
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3.4.2
SPI Timings The table below describes the requirements for devices connected to the SPI. The ATVaultIC460 SPI meets or exceeds these requirements under the noted conditions. See Figure 3-2 for details. Table 3-5.
See figure 9 10 11 12 13 14 15 16 17 18
SPI Timing Parameters
Description SS low to out SCK period SCK high/low Rise/Fall time Setup Hold SCK to out SCK to SS high SS high to tri-state SS low to SCK Condition Min Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max Unit ns ns ns ns ns ns ns ns ns ns
Figure 3-2.
SS
9
SPI Timings
10
16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MO SI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
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3.5 Connexions for Typical Application
Figure 3-3. ATVaultIC460 connexions for USB typical application
USB_XIN USB_XOUT 48 MHz RESONATOR
AT90SC6464C-USB ATVaultIC460
USB_DM USB CONNECTOR VBUS
C1 C2
GND USB_DP
Figure 3-4.
ATVaultIC460 connexions for I2C typical application
VCC VCC C1 C2 VCC GND RST VCC
HOST
RESET
ATVaultIC460
R2 SCL SDA
R1 SCL SDA / SPI_SEL
A0..A4
Address Selection
Figure 3-5.
ATVaultIC460 connexions for SPI typical application
VCC VCC C1 C2 VCC GND
ATVaultIC460 HOST
RESET RST SPI_SEL
MISO MOSI SS SCK
MOSI MISO SS SCK
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Figure 3-6.
ATVaultIC460 connexions for ISO7816 typical application
C1 C2 CVCC GND RESET
VCC GND RST
SC READER
I/O0 CLK
VCC
ATVaultIC460
R1 I/O0 CLK
Table 3-6. Configuration Reference
External components, Bill of Materials Description Typ.Value
48MHz 4.7 F 10 nF
Comment
Ceramic Oscillator USB C1 C2 R1, R2 I2C C1 C2 SPI C1 C2 R1 ISO7816 C1 C2 Power Supply Decoupling Capacitors Power Supply Decoupling Capacitors Pull-Up Resistors Power Supply Decoupling Capacitors Power Supply Decoupling Capacitors Power Supply Decoupling Capacitors Power Supply Decoupling Capacitors Pull-Up Resistor Power Supply Decoupling Capacitors Power Supply Decoupling Capacitors
Recommended Recommended Recommended Recommended Recommended Recommended Recommended usually on reader side usually on reader side usually on reader side
2.2 k
4.7 F 10 nF 4.7 F 10 nF
20 k
4.7 F 10 nF
3.5.1
Internal Oscillator characteristics The internal oscillator is optimized for a 48Mhz ceramic resonator oscillator. Table 3-7.
Code Vdd Vdd Idd on Freq Duty
Internal oscillator characteristics (T= -25C to +70C)
Condition Min. 1.4 rms value, 10kHz to 10Mhz External capacitors: 12pF 40 40 4.8 Typ. 1.8 Max. 2.0 30 7.1 48 60 Unit V mV mA MHz %
Parameter Supply voltage Supply ripple Current consumption Operating frequency Duty cycle
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Code Ton Pon ESR Cm Cshunt Cload Parameter Startup time Drive level Equivalent Serie Resistance Motional capacitance Shunt capacitance Load capacitance Max external capacitors: 12pF 2 @ 48Mhz @ 48MHz 10 Condition Min. Typ. Max. 1 500 70 200 6.2 6 1 Unit ms W fF pF pF A
Idd stdby Standby current consumption
The resonator must be placed as close as possible to the ATVaultIC460 chip. The oscillator terminals shall not be used to drive other circuits. In order to have the right resonator load capacitance, external capacitors must be connected on XIN and XOUT pins. For a given resonator, manufacturer specify a load capacitor value to add in parallel with the component. For a set of 2 caps connected between each oscillator terminal and ground, each of them should be equal to twice the specified load capacitance. Figure 3-7. External load capacitor
XIN
XOUT
XIN
XOUT
2*Cload Cload
2*Cload
Atmel recommends to use the ceramic resonator CERALOCK(R) from Murata with the part number CSTCW48M0X11Mxx-R0 (thin resonator for Smart Card) or CSTCZ48M0X11Rxx-R0 (small resonator for any system). This ceramic resonator hosts built-in capacitance in a small monolithic chip type. Its electrical properties best fit the Atmel specifications.
3.5.2
Building a USB Token A USB reference design is available for the ATVaultIC460 chip. Atmel offers a complete software and hardware solution based on a full USB communication stack, an ICCD compliant library and a USB dongle as target. The TPR0278 application note USB ICCD Implementation describes how to build a USB-ICC and how to implement an application based on the USB ICCD class.
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Figure 3-8.
USB Token schematic - Reference design
GPIO
GND
S1
22 21 20 19 18 17 16 15 14 13 12 QFN44 QFNSocket GPIO
J1
d0m 34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23
R1
1K
VCC
GND
VCC
D+
D-
Atmel
ATVaultIC460
D1
GND VCC
d0m 1 d0p 2
VCC
GND 3 4
d0p
C1
100nF
XOUT
RES
XIN 1 XIN GND 3 XOUT 2
Table 3-8.
Name S1 RES J1 C1 R1 D1
Bill Of Material - Reference design
Designation Microcontrollor in QFN44 package 48 Mhz ceramic resonator Plug USB Type A 100 nF capacitance 1K resistor Diode LED Constructor Ref Atmel ATVaultIC460 Murata CSTCW48M0X11xx Molex 48037-2000 KP-3216MGC
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GND
VCC
XIN
1 2 3 4 5 6 7 8 9 10 11
ATVaultIC460
3.6
3.6.1
Pin & Package Configuration
Pin Configuration Table 3-9. Designation QFN 44 SPI_SCK ISO_CLK USB_XOUT USB_XIN RST GPIO5 GPIO6 GPIO7 VCC GPIO0 MISO RTC_XOUT RTC_XIN VBAT MOSI GPIO1 GND GPIO2 SS / SCL 1 2 3 5 6 7 8 9 10,25,44 12 13 15 16 19 21 22 24 29 30 31 32 33 35 43 SOIC8/USB 6 7 8 1 2 3 4 5 SOIC8/SPI 5 6 7 8 1 2 3 4 SOIC8/ISO 5 7 8 1 2 3 4 SPI clock ISO7816 Clock Resonator Signal Input Resonator Signal Output CPU reset General Purpose IO 5 General Purpose IO 6 General Purpose IO 7 Power supply General Purpose IO 0 / IC Address SPI Master Input Slave Output Crystal signal Input Crystal signal Output Power Battery SPI Master Output Slave Input General Purpose IO 1 / IC Address Ground (reference voltage) General Purpose IO 2 / IC Address SPI Slave Select or IC SC SPI/IC selection PIN or IC SDA or ISO7816 IO0 General Purpose IO 3 / IC Address General Purpose IO 4 USB D- differential data USB D+ differential data Pin List Configuration Pin # Description
SPI_SEL / SDA / IO0 GPIO3 GPIO4 USB_DM USB_DP
Others pins are not connected (do not connect to GND).
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3.6.2
Pinouts for packages QFN44 and SOIC8 Figure 3-9. Pinout ATVaultIC460 - Package QFN44
USB_DM
37 42 41 39 38 36 40 35 34
44
SCK CLK USB_XOUT
43
USB_DP
VCC
1 2 3 4
INDEX CORNER
33 32 31 30
GPIO4 GPIO3 / IC Address IO0 / SPI_SEL /SDA SPI_SS /SCL GPIO2 / IC Address
USB_XIN RST GPIO5 GPIO6 GPIO7
5 6 7 8 9
EXPOSED PAD
29 28 27 26 25
VCC GND
VCC 10
11
ATVaultIC460
15 16 17 14 18 12 13 19 20 21 22
24 23
RTC_XIN
MISO
GPIO0 / IC Address
RTC_XOUT
VBAT
MOSI
Note: The exposed pad is connected to GND pin internally. So it is recommended to connect it to GND.
Figure 3-10. Pinout ATVaultIC460 - Package SOIC8 - USB configuration
GPIO1 / IC Address
GND
1
INDEX CORNER
8
VBUS
SPI_SS / I2C_SCL
2
ATVaultIC460 SOIC8 / USB
7
USB_XIN
ISO_IO0 / SPI_SEL / I2C_SDA
3
6
USB_XOUT
USB_DM
4
5
USB_DP
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Figure 3-11. Pinout ATVaultIC460 - Package SOIC8 - SPI and IC configurations
MOSI
1
INDEX CORNER
8
MISO
GND
2
ATVaultIC460 SOIC8 / SPI / IC
7
VCC
SCL / SS
3
6
RST
SDA / SPI_SEL
4
5
SCK
Figure 3-12. Pinout ATVaultIC460 - Package SOIC8 - ISO configuration
GND
1
INDEX CORNER
8
VCC
2
ATVaultIC460 SOIC8 / ISO7816
IO0
7
RST
3
6
4
5
CLK
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3.6.3
Packages characteristics Figure 3-13. SOIC-8 package characteristics
C
1
E
E1
N
L
?
Top View
End View
e A A1
SYMBOL
b
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A A1
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0 1.27 BSC
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8 4 2, 3 5 5
D
b C D E1 E L
?
Side View
e
Notes: 1. 2. 3. 4. 5.
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
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Figure 3-14. QFN-44 package characteristics
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Definitions and abbreviations
3DES / TDES AES APDU Authentication Triple DES algorithm Advanced Encryption Standard algorithm as defined in FIPS PUB 197 Application Protocol Data Unit as defined in ISO7816-3 An identification or entity authentication technique assures one party (the verifier), through acquisition of corroborative evidence, of both the identity of a second party involved, and that the second (the claimant) was active at the time the evidence was created or acquired. (From Handbook of Applied Cryptography) Application Specific Standard Product Cipher Block Chaining method applied to block ciphers Cipher Feedback Register chaining method applied to block ciphers Circuit(s) Cards Interface Devices Cipher-based Message Authentication Code Central Processing Unit A bit string used as a secret parameter by a cryptographic algorithm. To prevent a key from being guessed, keys need to be generated truly randomly and contain sufficient entropy. Data Encryption Standard algorithm as defined in FIPS PUB 46-3 Any CPU with master or slave capability Digital Signature Algorithm as defined in FIPS PUB 186-2 Electronic Code Book chaining method applied to block ciphers Elliptic Curves DSA as defined in FIPS PUB 186-2 Electrically Erasable Programmable Read-Only Memory File Allocation Table - file system from Microsoft(R) Federal Information Processing Standards An algorithm or technique that is specified or adopted in FIPS Hash-based Message Authentication Code as defined in FIPS PUB 198 Entity that communicates (directly or not) with the device. HMAC-based One Time Password algorithm as defined in RFC 4226 Smart Card interface Message Authentication Code - A bit string of fixed length, computed by a MAC generation algorithm, that is used to establish the authenticity and, hence, the integrity of a message. The device that initiates and terminates a transmission. The Master also generates the clock for synchronous interface. National Institute of Standards and Technology Non Volatile Memory (EEPROM, flash, ...)
ASSP CBC CFB CCID CMAC CPU Cryptographic key DES Device DSA ECB ECDSA EEPROM FAT FIPS FIPS-approved HMAC Host HOTP ISO7816 MAC Master NIST NVM
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OFB PC/SC RSA SCP SHA Slave SPI
Output Feedback Register chaining method applied to block ciphers Workgroup defining a standard architecture for integration of smart cards in computers Rivest Shamir Adleman algorithm Secure Channel Protocol as defined by GlobalPlatform Secure Hash Algorithm The device addressed by a master Serial Protocol Interface
Strong Authentication Exchange of messages during which a claimant proves its identity to a verifier by demonstrating its knowledge of a secret but without revealing it TWI / I2C USB Two Wire Interface and Inter Integrated Circuit Bus respectively Universal Serial Bus as defined in USB 2.0 standard
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Referenced Documents
[1] [2] [3] [4] [5] [6] ATMEL Corporation. AT98SO Generic Datasheet. TPR0395AX-July2009 (Availbale under Non-Disclosure Agreement signed with ATMEL). NIST SP 800-63 - Electronic Authentication Guideline - April 2006 ISO9798 - 2 Entity Authentication - Part 2 : Mechanisms using symmetric encipherment algorithms. July 1999 FIPS PUB 196. Entity Authenticationusing public key cryptography. Feb 1997. RSA Laboratories. PKCS #11 v2.20: Cyrptograhic Token Interface Standard. June 2004. Microsoft - Smart Card Minidriver Specification for Windows Base Cryptographic Service Provider (Base CSP) and Smart Card Key Storage Provider (KSP) version 5.07 September 2007 Atmel Corporation. How to secure Video Slot Gaming Machines using VaultICTM Security Modules? TPR443AX-September 2009 Universal Serial Bus Specification Revision 2.0. April 2000.
[7] [8]
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Datasheet Revision History
Rev AX - 15 July 2009 : Initial Version Rev BX - 29 September 2009 : Update Product Name
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1 Overview ................................................................................................... 3
1.1 1.2 1.3 1.4 1.5 1.6 Tampering resistance ........................................................................................3 Authentication capability ....................................................................................3 Secure storage ..................................................................................................4 Flexibility ............................................................................................................4 Typical application .............................................................................................5 Ordering Information ..........................................................................................5
1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 Legal ................................................................................................................. 5 Quotation and Volume ...................................................................................... 5 Part Number ...................................................................................................... 6 Starter Kit .......................................................................................................... 6 Demo Kit ........................................................................................................... 6
1.7
Software and Hardware Architecture .................................................................7
2
Detailed Features ..................................................................................... 8
2.1 2.2 Communication Interfaces .................................................................................8 Security Mechanisms ........................................................................................8
3
Product Characteristics ........................................................................ 10
3.1 3.2 3.3 3.4 Command Timings (T=25C) ...........................................................................10 Maximum Ratings ............................................................................................11 AC/DC Characteristics (2.7V - 5.5V range; T= -25C to +85C) .....................11 Timings ............................................................................................................13
3.4.1 3.4.2 IC Timings ...................................................................................................... 13 SPI Timings ..................................................................................................... 14
3.5
Connexions for Typical Application .................................................................15
3.5.1 3.5.2 Internal Oscillator characteristics .................................................................... 16 Building a USB Token ..................................................................................... 17
3.6
Pin & Package Configuration ...........................................................................19
3.6.1 3.6.2 3.6.3 Pin Configuration ............................................................................................ 19 Pinouts for packages QFN44 and SOIC8 ....................................................... 20 Packages characteristics ................................................................................ 22
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 01-05 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support at98sc@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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